The present invention relates in general to data processing systems, and in particular, to burst instruction transfers from I/O subsystems in data processing systems.
In a modem data processing systems, a stream of instructions is often transferred from main memory into a cache memory in a burst read operation. The burst read transfers a plurality of instruction xe2x80x9cwordsxe2x80x9d which fills a cache line. (An instruction xe2x80x9cwordxe2x80x9d includes a predetermined number of bits which constitute the instruction, which number of bits may be depend on the processor implementation.) Burst instruction transfers from a subsystem designed and optimized for transfers on word boundaries and a system bus designed and optimized for transfers on double word boundaries may give rise to misaligned reads. This may typically occur through devices that interface to the system bus through an input/output (I/O) subsystem. Exemplary implementations in which an instruction stream may be accessed through an I/O subsystem include initial program load read-only storage (IPLROS) and initialization or diagnostic code resident on I/O adapters.
Typically, to prevent misaligned reads, the I/O subsystem must be selected to be compatible with the system bus. This complicates the development of data processing system, particularly, as processor technology advances rapidly with a concomitant increase in system bus widths. Thus, there is a need in the art for a mechanism to align instruction reads across otherwise incompatible subsystems on a system bus.
The aforementioned needs are addressed by the present invention. Accordingly, there is provided, in a first form, a burst transfer alignment method. The method includes invalidating a cache line, in which the cache line includes at least one entry containing a predetermined data value representing an invalid instruction, the predetermined data value being loaded in response to detecting an unaligned read. The cache line is refetched at the address of the invalid instruction whereby an aligned transfer of the refetched line is effected.
There is also provided, in a second form, a data processing system. The system contains circuitry operable for invalidating a cache line, wherein the cache line includes at least one entry containing a predetermined data value representing an invalid instruction. System circuitry loads the predetermined data value in the cache line in response to circuitry operable for detecting an unaligned read. Also included is circuitry operable for returning to a selected one of the at least one entry containing an invalid instruction. A refetch of the invalidated cache line generates an aligned transfer.
Additionally, there is provided, in a third form, a computer program product operable for storage in machine readable storage media, the program product operable for burst transfer alignment. The program product includes programming for invalidating a cache line, wherein said cache line includes at least one entry containing a predetermined data value representing an invalid instruction. The program product also has programming for returning to a preselected one of said at least one entry containing an invalid instruction. A refetch of the invalidated cache line generates an aligned transfer.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.